MapBuf: Simultaneous Technology Mapping and Buffer Insertion for HLS Performance Optimization

MapBuf integrates buffer insertion with technology mapping for dataflow circuits generated by high-level synthesis, so buffering decisions see true post-mapping timing. Best Paper Award nominee at IWLS and ICCAD 2023.

Hanyu Wang, Carmine Rizzi, Lana Josipović · ICCAD 2023 · Best Paper Award nominee (IWLS & ICCAD 2023) · DOI · PDF

Plain-language summary

Dataflow (dynamically scheduled) circuits produced by high-level synthesis need buffers to run at a high clock frequency, but deciding where to put buffers requires knowing gate-level timing — which is only accurate after technology mapping. Doing the two steps separately forces conservative delay estimates and leaves performance on the table: buffers placed early invalidate the timing assumptions that mapping later relies on. MapBuf solves both problems together in a single formulation, so buffer placement decisions are driven by true post-mapping delays. The approach is open source and integrated into the Dynamatic HLS compiler from EPFL/ETH.

Key contributions

  • A unified formulation that performs technology mapping and buffer insertion simultaneously for HLS-generated dataflow circuits.
  • Buffer placement driven by accurate post-mapping timing instead of conservative pre-mapping estimates.
  • Open-source implementation integrated into the Dynamatic HLS framework.

Key results

Compared to state-of-the-art flows that handle buffering and technology mapping separately, MapBuf achieves an average improvement of 13.32% in execution time and 11.14% in area.

Resources

How to cite

@inproceedings{wang2023mapbuf,
  author    = {Wang, Hanyu and Rizzi, Carmine and Josipovi{\'c}, Lana},
  title     = {MapBuf: Simultaneous Technology Mapping and Buffer Insertion for HLS Performance Optimization},
  booktitle = {IEEE/ACM International Conference on Computer-Aided Design (ICCAD)},
  pages     = {1--9},
  publisher = {IEEE},
  year      = {2023}
}